1. Field of the Invention
This invention relates to improved trench formation in semiconductor devices and, more specifically, to minimization of stress on trench wall insulation.
2. Brief Description of the Prior Art
It is well known in the semiconductor art to isolate adjacent active or moat regions from each other by means of a trench. A trench is a groove in a semiconductor substrate which has an insulating sidewall, generally formed from a layer of silicon oxide and a layer of silicon nitride, and is generally refilled with polysilicon up to the level of the substrate surface. Conventional polysilicon refilled trench isolation for bipolar or CMOS circuits has several problems in the areas of defect generation and void formation. Void formation and/or peculiar topography occurs when both the interior and exterior of the trench surfaces are oxidized. Detailed discussions of the problem appear in IEDM '84 conferences which are published at IEDM Technical Digest, pages 586, 1984. Defect generation is particularly noticeable during oxidation of the surface of the device with a polysilicon filled trench wherein both the substrate and the polysilicon form oxides and expand against the, trench wall insulating layer, thereby placing a stress on the insulating side walls of the trench as well as on the junction of the oxides formed in conjuction with the polysilicon and substrate.
A solution to the above noted problem to eliminate the defect generation has been reported wherein oxide/nitride dielectrics are used in the trench before the polysilicon is deposited. The structure is known as Sealed Sidewall Trench (SST) isolation and is disclosed in U.S. Pat. No. 4,631,803. However, SST is complex. Besides, notches or grooves may still exist at the junction between the field oxide which is grown over the polysilicon in the trench and the field oxide which is grown over the single crystal silicon outside the trench.